1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various novel methods of forming reduced thickness sidewall spacers in CMOS based integrated circuit products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. A so-called metal oxide field effect transistor (MOSFETs or FETs) is one commonly employed circuit element that is found on integrated circuit products. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of carriers (n- or p-type) in channel with consistent dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices.
Irrespective of the physical configuration of the transistor device, each device comprises spaced-apart drain and source regions formed in a semiconductor substrate and a gate structure positioned above the substrate and between the source/drain regions. The gate structure is typically comprised of a relatively thin gate insulation layer (e.g., silicon dioxide or a high-k insulating material) positioned on the substrate between the source/drain regions and one or more conductive materials (e.g., polysilicon, one or more metal layers, etc.) that serve as the gate electrode for the device. A gate cap layer (e.g., silicon nitride) is formed above the gate structure and a sidewall spacer (e.g., silicon nitride) is formed adjacent the sidewalls of the gate structure. The gate cap layer and the sidewall spacer are provided to electrically isolate the gate structure and protect the gate structure during subsequent processing operations that are preformed to complete the device. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region. The gate structures for such transistor devices may be manufactured using so-called “gate-first” (i.e., wherein the gate structure is formed before the source/drain regions are formed) or “replacement gate” (gate-last) (i.e., wherein the final gate structure is formed after the source/drain regions are formed) manufacturing techniques.
FIG. 1 depicts an illustrative prior art semiconductor product 10 comprised of first and second transistors 11A, 11B formed in and above the substrate 12. Each of the transistors 11A, 11B is comprised of a schematically depicted gate structure 13 (which includes the gate insulation layer and gate electrode that are not separately depicted), a gate cap layer 14 and a sidewall spacer 15. Also depicted are illustrative raised source/drain regions 18 and a plurality of self-aligned contacts 20 that are positioned in a layer of insulating material 19, e.g., silicon dioxide. The self-aligned contacts 20 are conductively coupled to the raised source/drain regions 18. The spacers 15 are typically made of silicon nitride which has a relatively high k value of, e.g., about 7-8. As a result of the structure of the transistors, a gate-to-contact capacitor is generally defined in the dashed-line regions 21, where the gate electrode of the gate structure 13 functions as one of the conductive plates of the capacitor and the self-aligned contact 20 functions as the other conductive plate of the capacitor. In other cases, the contact 20 may be formed by performing traditional lithography/etching processes, i.e., portions of such traditionally formed contact 20 (not shown in FIG. 1) may not be positioned above a portion of the spacer 15. The presence of the silicon nitride spacer material (with a relatively high k value) tends to increase the parasitic capacitance between the conductive gate electrode and self-aligned contacts. This problem has become even more problematic as packing densities have increased, which causes the gate structures of adjacent transistors to be positioned ever closer to one another (thus, the “self-aligned” contact structure 20 with contact metal in direct contact with the spacer 15, as illustrated in FIG. 1, is one technique used in advanced CMOS products). Unfortunately, the gate-to-contact capacitor tends to slow down the switching speed of the transistor as this capacitor must be charged and discharged each time the transistor is turned on-off.
The use of alternative materials for the sidewall spacers, such as materials having k values less than about 7.0 (i.e., lower than the k value of silicon nitride), has been desirable but often problematic. Most of such low-k materials are based upon carbon or boron doped silicon nitride (other examples include spacers comprised of organosilicate glass (OSG), fluorine doped SiO2, carbon doped SiO2, porous SiO2, porous carbon doped SiO2, spin-on organic polymeric dielectrics, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ) or combinations of such materials) and they are often porous in nature and may have pin-holes. The low-k material, when used as a traditional spacer material, is subjected to subsequent process steps, e.g., wet cleans, ion implantation, a reactive ion etching (RIE) process, etc., in order to define the position where the source/drain regions will be located. These post-spacer formation processing steps tend to deplete the carbon and boron, thereby effectively increasing the k value of the low-k material. Such low-k materials also tend to be weaker mechanically than silicon nitride, which makes them less capable of standing up to the subsequent processing steps (to serve as barriers to contaminants and moisture) after they are formed, e.g., wet cleaning processes, etching processes, etc. For example, such low-k spacers are difficult to integrate into process flows involving the formation of epi materials in the source/drain regions of the devices (e.g., epi SiGe for PMOS devices and epi-SiC for NMOS devices) due to the cleaning processes and the RIE cavity etching processes performed prior to the epi growth process and the unwanted growth of the epi materials on the low-k spacers. Moreover, such spacers are typically subjected to ion implantation with relatively high temperature source/drain anneal processes, which also tends to damage and deplete the carbon and boron from such low-k materials.
FIGS. 2A-2C depict one illustrative prior art technique that device designers have employed in an attempt to incorporate low-k spacers into integrated circuit products. FIG. 2A depicts a transistor device 50 at an advanced stage of fabrication that has been formed in and above a semiconductor substrate 51. As shown therein, the transistor 50 is comprised of a simplistically depicted gate structure 53 (which includes a gate insulation layer 53A and gate electrode 53B), a silicon dioxide liner layer 52, a gate cap layer 55 and a silicon nitride sidewall spacer 54. The silicon nitride spacer 54 is conventionally used as a diffusion barrier for protecting the materials of the gate structure 53 from contaminants and moisture. The silicon dioxide liner layer 52 serves as a buffer layer between the silicon nitride spacer 54 and materials of the gate structure 53. Also depicted are illustrative source/drain regions 56 and metal silicide regions 58. At the point of processing depicted in FIG. 2A, the transistor 50 is basically complete. However, with reference to FIG. 2B, to incorporate a low-k spacer into the finished device (for achieving a lower capacitance between the gate structure 53 and the source/drain contact structures (not shown in FIGS. 2A-2C)), an etching process was performed to selectively remove the silicon nitride sidewall spacer 54 relative to the surrounding materials. Then, as shown in FIG. 2C, a low-k sidewall spacer 60 was formed on the device 50 to essentially replace the silicon nitride sidewall spacer 54. The low-k spacer 60 was formed by depositing a layer of low-k material and thereafter performing an anisotropic etching process as is well known to those skilled in the art. The spacer 60 may be formed selectively in the N and P regions of the product using known lithography and etching techniques. In some cases, the low-k spacer 60 may be made of a silicon nitride material with added carbon and/or oxygen (e.g., SiOCN). Low-k spacers of such materials tend to function well as barriers to contaminants and moisture, tend to be pin-hole free, and also have a lower k value than that of traditional silicon nitride spacers (e.g., about 7.8).
FIGS. 3A-3L depict one illustrative prior art technique for forming CMOS based products that involves the formation of a number of spacers and the formation of epi semiconductor material in the source/drain regions of the devices. In the remaining drawings in this application, the various spacers that are formed will be depicted as simply rectangular shaped structures so as not to overly complicate the drawings. In a real world device, the sidewall spacers will have more of a curved outer surface like that of the spacers 54 and 60 depicted in FIGS. 2A-2C wherein the spacers tend to be thicker at the base of the spacer and thinner as one progresses up the height of the spacers. The spacers may also have an irregular outer surface like that of the spacers 15 depicted in FIG. 1 (after performing self-aligned contact litho/etching processes). Moreover, to the extent reference is made to a thickness of a spacer in this application, it will refer to the thickness of the spacer at the base of the spacer. Additionally, the formation of transistors typically involves performing one or more ion implantation processes at various points in the process flow to form various doped regions in the substrate, such as halo implant regions, extension implant regions (or LDD implant regions) and deep source/drain implant regions. In many of the cases, one or more spacers are formed adjacent the gate structure so as to control the location of the various implant regions and/or to control the location where cavities may be formed in the source/drain regions of the NFET and PFET devices, wherein different stressed epi semiconductor materials will be formed in the cavities of the NFET and PFET devices. However, so as not to overly complicate the attached drawings, the various doped regions that are found in transistor devices are not depicted in the drawings.
FIGS. 3A-3L depict one illustrative prior art process flow for forming a CMOS integrated circuit product 100 that includes an illustrative PMOS transistor 100P and an illustrative NMOS transistor 100N using an illustrative combination of spacers. As shown in FIG. 3A, the process begins with the formation of illustrative gate structures 114 for the PMOS transistor 100P and the NMOS transistor 100N in and above regions of the substrate 101 that are separated by an illustrative shallow trench isolation structure 112 (not to scale—just for illustrative purposes). The gate structures 114 generally include a gate insulation or gate dielectric layer 114A and one or more conductive gate electrode layers 114B. A gate cap (or hard mask) layer 116, made of a material such as silicon nitride, is formed above the gate structures 114. Also depicted in FIG. 3A is an illustrative layer 117, made of a material such as silicon dioxide, e.g., a pad oxide layer. The gate structures 114 depicted herein are intended to be schematic and representative in nature, as the materials of construction used in the gate structures 114 may be different for the PMOS transistor 100P as compared to the NMOS transistor 100N (for individually tuning the work-function for the NMOS and PMOS devices), e.g., the thickness of the multiple layers of conductive metal in the gate 114B may be different for the PMOS transistor 100P and the NMOS transistor 100N, etc. The gate insulation layer 114A may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a high-k (k value greater than 10) insulating (dielectric) material. The gate electrode layer 114B may be comprised of one or more layers of conductive materials, such as polysilicon, a metal-nitride (e.g., TiN, TaN), a metal (e.g., Al or W), etc. The gate structure depicted in FIG. 3A may be formed by performing a variety of known techniques. For example, using a so-called “gate first” manufacturing technique, the layers of material that make up the gate insulation layer 114A, the gate electrode layer 114B and the gate cap layer 116 may be blanket-deposited above the substrate 101 and, thereafter, one or more etching processes are performed through a patterned mask layer (not shown) to define the basic gate structures depicted in FIG. 3A. Of course, the gate structures 114 could also be sacrificial gate structures in the case where a replacement gate process is used to manufacture the product 100, wherein a replacement gate structure is formed after the source/drain regions of the device are completed. FIG. 3A also depicts the product 100 after a sidewall spacer 118 (“spacer 1”), typically made of traditional silicon nitride or low-k spacer SiOCN, was formed adjacent the gate structures 114 of both the PMOS transistor 100P and the NMOS transistor 100N. Typically, a thin interfacial silicon dioxide layer (not shown) may be formed on the gate structures 114 prior to the formation of the spacer 118. The spacer 118 may have an illustrative base width of about 10-12 nm in advanced 20 nm CMOS technology products. The spacer 118 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching back process. After the spacer 118 is formed, various ion implant processes may be performed on the devices 100N, 100P, respectively, through patterned implant masks.
FIG. 3B depicts the product 100 after several process operations were performed to form a PMOS sidewall spacer 120P (“spacer 2”) adjacent the spacer 118 of the PMOS transistor 100P. First, a layer of spacer 2 material 120L was deposited above both the PMOS transistor 100P and the NMOS transistor 100N. Thereafter, an etch mask layer 121, such as photoresist, was formed so as to cover the NMOS transistor 100N while exposing the PMOS transistor 100P. Next, an anisotropic etching process was performed on the exposed portion of the layer of spacer 2 material 120L so as to define the PMOS sidewall spacer 120P (spacer 2 for the PMOS device). The PMOS sidewall spacer 120P may have an illustrative base width of about 10-20 nm. The layer of spacer 2 material 120L may be made of a material such as silicon nitride and it may be formed to any desired thickness.
FIG. 3C depicts the product 100 after an anisotropic etching process was performed through the etch mask layer 121 to remove exposed portions of the layer 117 on the PMOS transistor 100P.
FIG. 3D depicts the product 100 after several process operations were performed on the product 100. First, the etch mask layer 121 was removed by performing an ashing process. Thereafter, one or more etching processes (Si) were performed to define PMOS source/drain cavities 124 in areas of the substrate 101 where source/drain regions for the PMOS transistor 100P will ultimately be formed by forming a compressively stressed epi semiconductor material in the PMOS source/drain cavities 124. The depth and shape of the PMOS source/drain cavities 124 may vary depending upon the particular application. In one example, the PMOS source/drain cavities 124 may have an overall depth of about 50-70 nm.
FIG. 3E depicts the product 100 after an epitaxial growth process was performed to form compressively stressed epitaxial semiconductor material regions 126 (e.g., silicon germanium regions) in the PMOS source/drain cavities 124 for the PMOS transistor 100P. In the depicted example, the regions 126 have an upper surface that is substantially level with the upper surface of the substrate 101. In other cases, the epi semiconductor material 126 may be formed in such a manner so that it overfills the cavities 124 and its upper surface is positioned at a level that is above the upper surface of the substrate 101 (e.g., raised source/drain regions—not illustrated in FIG. 3E for simplicity) by about 10-20 nm. The epi regions 126 may be formed by performing well known epitaxial growth processes and they may be made of a material such as SiGe (with Ge content ˜20-50%) so as to induce a compressive stress in the channel region of the PMOS transistor 100P and thereby enhance its current carrying capabilities. Note that the layer of spacer 2 material 120L remains positioned on the NMOS transistor 100N during the cavity etching process and the epi growth process.
FIG. 3F depicts the product 100 after several process operations were performed. First, a layer of spacer 3 material 122L was deposited above both the PMOS transistor 100P and the NMOS transistor 100N. Thereafter, an etch mask layer 123, such as photoresist, was formed so as to cover the PMOS transistor 100P while exposing the NMOS transistor 100N. The layer of spacer 3 material 122L may be made of a material such as silicon nitride and it may be formed to any desired thickness.
FIG. 3G depicts the product 100 after one or more etching processes were performed through the etch mask 123 on the spacer 3 and spacer 2 material layers 122L, 120L, respectively, to form a spacer structure comprised of an NMOS sidewall spacer 120N (“spacer 2”) and an NMOS sidewall spacer 122N (“spacer 3”) adjacent the spacer 118 (spacer 1) of the NMOS transistor 100N. The NMOS sidewall spacer 122N may have an illustrative base width of about 10-20 nm.
FIG. 3H depicts the product 100 after an anisotropic etching process was performed through the etch mask layer 125 to remove exposed portions of the layer 117 on the NMOS transistor 100N.
FIG. 3I depicts the product 100 after several process operations were performed on the product 100. First, the etch mask layer 125 was removed by performing an ashing process. Thereafter, one or more etching processes were performed to define NMOS source/drain cavities 142 in areas of the substrate 101 where source/drain regions for the NMOS transistor 100N will ultimately be formed by forming a tensile stressed epi semiconductor material in the NMOS source/drain cavities 142. The depth and shape of the NMOS source/drain cavities 142 may vary depending upon the particular application. In one example, the NMOS source/drain cavities 142 may have an overall depth of about 50-70 nm.
FIG. 3J depicts the product 100 after an epitaxial growth process was performed to form tensile stressed epitaxial semiconductor material regions 144 (e.g., silicon carbon regions) in the NMOS source/drain cavities 142 for the NMOS transistor 100N. In the depicted example, the regions 144 have an upper surface that is substantially level with the upper surface of the substrate 101. In other cases, the epi semiconductor material 144 may be formed in such a manner so that it overfills the NMOS source/drain cavities 142 and its upper surface is positioned at a level that is above the upper surface of the substrate 101 (e.g., raised source/drain regions) by about 10-20 nm. The epi regions 144 may be formed by performing well known epitaxial growth processes of, for example, a material such as SiC (with C content ˜1-2%) so as to induce a tensile stress in the channel region of the NMOS transistor 100N and thereby enhance its current carrying capabilities. Note that the layer of spacer 3 material 122L remains positioned on the PMOS transistor 100P during the cavity etching process and the epi growth process.
FIG. 3K depicts the product 100 after an etch mask layer 125, such as photoresist, was formed so as to cover the NMOS transistor 100N while exposing the PMOS transistor 100P.
FIG. 3L depicts the product 100 after several process operations were performed on the product 100. First, an anisotropic etching process was performed on the exposed portion of the layer of spacer 3 material 122L so as to define a PMOS sidewall spacer 122P (spacer 3 for the PMOS device). The PMOS sidewall spacer 122P may have an illustrative base width of about 10-20 nm. Next, an ashing process was performed to remove the masking layer 125.
In the above-described process flow, each of the devices 100P, 100N are comprised of three spacers 118, 120 and 122. Unfortunately, the final combined thickness of the three spacers 118, 120 and 122 (considered collectively) is still relatively large and they were exposed to several post-formation processing steps (e.g., RIE, implants, wet clean, etc.) and were accordingly damaged. Portions of the spacer 120 are positioned above the epi regions 126 in the PMOS device 100P thereby making it more difficult (a smaller process window) to accurately land a contact structure to the source/drain regions of the PMOS device. Additionally, the presence of the spacer 120 (e.g., SiCON) can be problematic in that the spacer 120 interacts with the formation of the epi material regions 126 and 144, and the spacer 120 may exhibit more defects (e.g., pin holes) and suffer from inconsistent thickness variations when it is subjected to epi pre-clean processes and the presence of the spacer 120 can cause undesirable non-uniform loading of one or more of the epi growth processes.
What is needed is a new process flow for forming CMOS devices that, in some cases, can incorporate low-k spacers into the process flow in an efficient a manner. The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.